Input



Re. 25,2 62 ING 1962 G. D. BRUCE ET AL BINARY TRIGGER AND COUNTERCIRCUITS EMPLOY MAGNETIC MEMORY DEVICES 31, 1953 3 Sheets-Sheet 1Original Filed Dec.

w m f v INVENTORS GEORGE D BRUCE D. BRUCE ET AL Oct. 16, 1962 G BINARYTRIGGER AND COUNTER CIRCUITS EMPLOYING MAGNETIC MEMORY DEVICES 3Sheets-Sheet 2 Original Filed Dec. 31, 1955 i z. T 1 35a 36c INVENTORSGFOPGE 0 BAZ/CE BY M035 6 C. [0664 A21; )LM

ATTOE/VEV Oct. 16, 1962 G, D. BRUCE ET AL Re. 25,262

BINARY TRIGGER AND COUNTER CIRCUITS EMPLOYING MAGNETIC MEMORY DEVICESOriginal Filed Dec. 31, 1953 5 Sheets-Sheet 3 //VPU7 S/G/VALS TK lf f fm EEE E EEE az/m/r F1 47 www/va 52 f our/ 07 ,se 66* 47 I/W/VD/A/G 32OUT/ 07' 68 AT I/W/VD/NG s2 IN V EN TORS syizhiw ATTGE/VEV Unite Statesatent Re. 25,262 Reissued Oct. 16, 1962 25,262 BINARY TRIGGER ANDCOUNTER CIRCUITS EM- PLOYING MAGNETIC MEMORY DEVICES George D. Bruce andJoseph C. Logue, Poughkeepsie,

N .Y., assignors to International Business Machines Corporation, NewYork, N .Y., a corporation of New York Original No. 2,772,370, datedNov. 27, 1956, Set. No. 401,674, Dec. 31, 1953. Application for reissueJan. 2,

1958, Ser. No. 710,829

4 Claims. (Cl. 307-88.5)

Matter enclosed in heavy brackets appears in the original patent butforms no part of this reissue specification; matter printed in italicsindicates the additions made by reissue.

This invention relate to binary trigger circuits employ ing magneticmemory devices and counter circuits utilizing such binary triggercircuits.

A binary trigger circuit may be defined as a circuit which responds totwo successive input pulses of the same olarity to produce a Singleoutput pulse. Each output pulse may therefore be said to count a pair ofinput pulses.

A counter circuit may be defined as one which produces an Output pulsecorresponding to a given number of input pulses. By definition,therefore, a binary trigger circuit is a sort of counter circuit. Binarytrigger circuits may be cascaded so that each stage in the cascadecounts the output pulses from the preceding stage. If each stage isbinary, then each succeeding stage provides a binary count of a higherorder than the preceding stage. For example,

the first stage counts by twos, the second by fours, the

third by eights, and so on. A decimal counter circuit is one whichproduces an output pulse at the end of each series of ten Successiveinput pulses.

It has been proposed to provide a decimal counter circuit comprising anumber of binary stages coupled together. Such a decimal counter isdisclosed, for example, in the United States patent to Phelps, No.2,584,811.

Transistors have recently become popular as electrical translatingdevices, especially in connection with high speed electrical computers,where their low power and low voltage requirements provide a tremendousadvantage in installations which may employ thousands of suchtranslating devices. Such computers may employ many binary circuits andcounters of the type described.

Binary trigger circuits have been proposed using transistors. Suchcircuits have been of the regenerative type, using a feedback from theoutput to the input, and have two stable output states, separatedsubstantially as to current and potential values, being triggered backand forth I between their two output states in response to inputsignals. In such a circuit, the transistor is typically continuouslyconductive, either at a high or low current. When shifting from a highcurrent state to a low current state, such trigger circuits may besubject to difliculties due to a hole storage in the transistor, forexample, an increased fall time or delay in reaching the low currentstate. This continuous current may be considered as forming a memory ofthe last received signal and represents a substantial energy requirementwhich might be avoided by using pulse type signals and outputs and amemory device not requiring power.

Where it is desired to couple transistor binary trigger circuits inmultiple stage arrangements, a further difiiculty is presented in thattransistors commonly have emitter input impedances much lower than theircollector output impedances, so that special provisions are required forimpedance matching between stages. Among the memory devices in currentuse, e.g., in the high speed computers previously mentioned, aremagnetic memory devices which operate by magnetizing a core to the pointof saturation in one direction. The state of polarization of the core isthen utilized later to read the signal which was stored in the memorydevice by the polarizing action. The stored information is retainedindefinitely, until the state of magnetization of the core is changed bypositively reversing it. Such magnetic memory devices have beenconstructed having low power and voltage requirements of the same orderas the corresponding requirements of transistors.

An object of the present invention is to provide a binary triggercircuit employing a magnetic memory device to retain the impression ofthe last received signal.

Another object of the invention is to provide a multiple stage countercircuit including in each stage a magnetic memory device for retainingthe impression of previously received signals.

A further object of the present invention is to provide circuits of thetype described employing transistors.

Another object is to provide a binary trigger circuit employingtransistors, and producing a pulse type output signal, rather than asteady output signal.

Another object is to provide a binary trigger circuit employingtransistors and having improved impedance matching characteristics.

The foregoing and other objects are attained in the circuits describedherein by providing a binary trigger stage including a saturablemagnetic core having two driving windings and two feedback windings. Twoamplifiers are provided for each stage, each amplifier having onedriving winding connected in its output circuit and one feedback windingconnected in its input circuit. Each amplifier, in the modificationsshown and described, includes a transistor. Both amplifiers receivepulse signals from a common input. The pulse output signals are derivedfrom a special output winding on the saturable core. The design of thiswinding may be varied as required for impedance matching purposes.

In the multiple stage counter circuit described herein, four binarytrigger stage are connected in cascade. The first three stages arebinary stages so that the third stage counts eight input pulses. Thefourth stage is connected to count two additional input pulses after theeighth so that the output of the fourth stage provides a count of teninput pulses.

Other objects and advantages of our invention will become apparent froma consideration of the following specification and claims, takentogether with the accompanying drawings.

In the drawings:

FIGURE 1 is a wiring diagram of a binary trigger circuit embodying theinvention.

FIGURE 2 is a wiring diagram of a modified form of binary triggercircuit embodying the invention.

FIGURE 3 is a wiring diagram of still another modified form of binarytrigger circuit embodying the invention.

FIGURE 4 is a wiring diagram of a decimal counter circuit embodying theinvention.

FIGURE 5 illustrates graphically the input signals and the signals atthe outputs of the several stages in the circuit of FIG. 4.

FIGURE 1 There is shown in FIGURE 1 a binary trigger circuit including amagnetic memory device generally indicated at 1 and having a saturablemagnetic core 2, driving windings 3 and 4, feedback windings 5 and 6,and an output Winding 7. The saturable core 2 is illustrated onlydiagrammatically in FIG. 1. It will be understood that a closed ringcore is preferred, in accordance with the usual practice in suchdevices.

Two amplifiers 8 and 9 are connected to the magnetic memory device 1.The amplifier 8 includes a transistor 10 of the PNP junction type,having an emitter electrode c, a collector electrode 10c and a baseelectrode 10b. Amplifier 9 similarly includes a PNP junction transistor11 having an emitter electrode 11e, a collector electrode 11c, and abase electrode 11b. v

The input circuits of both amplifiers 8 and 9 receive signals from apair of input terminals 12 and 13 through an input transformer 14 havinga primary winding 15 and a secondary winding 16.

The input circuit of amplifier 8 may be traced from emitter electrode10e through secondary winding 16, wires 17, 18 and 19, and feedbackwinding 5 to base electrode 10b. The input circuit for amplifier 9 maysimilarly be traced from emitter electrode 11e through secondary winding16, wires 17 and 18 and feedback winding 6 to base electrode 11b.

The output circuit of amplifier 8 may be traced from collector electrode10c through driving winding 3, battery 20, wires 18 and 19, and feedbackwinding 5 to base electrode 10b. The output circuit of amplifier 9 maysimilarly be traced from collector electrode 11c through driving winding4, battery 20, wire 18 and feedback winding 6 to base 11b.

Output winding 7 is connected to output terminals 22 and 23 through anasymmetric impedance device 24.

OPERATION OF FIGURE 1 It should be observed that the driving windings 3and 4 are connected so that currents of the same polarity flowingthrough them tend to magnetize the core 2 in opposite senses.Furthermore, the feedback windings 5 and 6 are connected so that thepotentials induced in them by a change in current in their respectivelyassociated driving windings 3 and 4, act on the input circuits of therespective transistors 10 and 11 in a sense to increase the emittercurrents thereof, and thereby act cumulatively to increase the collectorcurrent flow in the winding 3 or 4, as the case may be. In other words,the windings 5 and 6 provide positive feedbacks from windings 3 and 4 [2and 3], respectivel to the amplifiers 8 and 9 respectively.

Considering the operation of the amplifier 8 alone (i.e., assumingamplifier 9 and its windings to be absent), then beginning with the core2 demagnetized, a signal impressed on the amplifier input circuit willproduce a current flowing continuously in the winding 3 and continuouslyincreasing until a point is reached at which the core 2 is saturated. Atthat point, the coupling between the driving winding 3 and the feedbackwinding 5 is greatly reduced, and the amplifier is substantially cutoff.

Both amplifiers are normally connected to their respective windings onthe magnetic memory device, both are normally cut off and the core 2 isnormally magnetically saturated in one direction or the other. When aninput signal is received at terminals 12 and 13, both amplifiers 8 and 9respond by sending currents through the driving windings 3 and 4. Sincethe core 2 is already saturated in one direction, the current throughone of the driving windings is substantially ineffective to change themagnetic condition of the core, and consequently the amplifierassociated with that driving winding receives no feedback impulse and iscut oif. On the other hand, the current flowing in the other drivingwinding is effective to decrease the magnetization of the core. Thischange in the magnetization of the core produces a potential in theassociated feedback winding in the proper direction to amplify thecurrent in the driving winding. This cumulative process continues untilthe polarity of the core 2 is reversed and the core is saturated in theopposite direction. The driving amplifier is then cut off.

When the next impulse is received at the input terminals 12 and 13,there will again be only one of the two driving windings which iseffective. However, it will be the driving winding which was noteffective during the preceding impulse. Consequently, there will appearin the output winding 7 an output potential pulse for each inputpotential pulse at the input terminals 12 and 13, but the outputpotentials in the winding 7 will be alternately of opposite polarities.By connecting the asymmetric impedance unit 24 in series with thewinding 7, the output signals of one polarity are suppressed so thatonly alternate output signals appear at the terminals 22 and 23.Consequently, the output signals provide a binary count of the inputsignals received at input terminals 12 and 13.

It should be noted that the output signals are pulses of limitedduration, and that after each output signal, the amplifiers are bothrestored to their cut off condition.

The design of winding 7 may be varied as required for impedance matchingpurposes.

FIGURE 2 This figure illustrates a modified form of binary triggercircuit, in which the input circuits are connected in a somewhatdifferent manner than in the circuit of FIG. 1. Specifically, theamplifiers are provided with base inputs rather than emitter inputs. Thecircuit and its operation are otherwise substantially the same as inFIG. 1

In view of the close relationship between the circuits of FIGS. 1 and 2,each circuit element in FIG. 2 has been given the same reference numeralas its counterpart in FIG. 1 and the circuit of FIG. .2 will not befurther described.

FIGURE 3 This figure illustrates a modified form of trigger circuitemploying the principles of the invention. In this circuit there isillustrated a magnetic memory device 26, including a saturable ring core27 on which are provided two driving windings 28 and 29, two feedbackwindings 30 and 31, and an output winding 32.

Two amplifiers 33 and 34 are provided. The amplifier 33 includes a pointcontact transistor having a body 35 of n-type semi-conductive material,an emitter electrode 35c, a collector electrode 35c and a base electrode35h. Similarly, the amplifier 34 includes a transistor having a body 36of n-type semi-conductive material, an emitter electrode 36c, acollector electrode 36c and a base electrode 36b.

The input circuit of amplifier 33 may be traced from emitter 35c througha resistor 37, a battery 38, battery 39, secondary winding 40 of aninput transformer 41, wire 42 and feedback winding 30 to base electrode35b. An asymmetric impedance unit 43 is connected between emit terelectrode 35c and ground.

The input circuit for amplifier 34 may be traced from emitter electrode36c through wire 44, resistor 37, batteries 38 and 39, secondary winding40, wire 45 and feedback winding 31 to base electrode 36b.

The input transformer 41 is provided with a primary winding 46 connectedto input terminals 47 and 38.

The output circuit of amplifier 33 may be traced from collectorelectrode 35c through driving winding 28, battery 49, battery 39,secondary winding 40, wire 42, and feedback winding 30 to base electrode35b. The output circuit of amplifier 34 may similarly be traced fromcollector 36c through driving winding 29, battery 49, battery 39,secondary winding 40, wire 45, and feedback winding 31 to base electrode36b.

Output winding 32 is connected to output terminals 50 and 51.

OPERATION OF FIGURE 3 The circuit of FIG. 3 and its operation aregenerally analogous to those in FIGS. 1 and 2, except for the novelbiasing arrangement for the two input circuits, including battery 38,resistor 37 and asymmetric impedance unit 43. These three circuitelements form a closed loop whose function is to supply, to the twoemitters 35c and 36e, a constant amount of current which is suflicientto maintain only one of the two amplifiers 33 and 34 in its Oncondition. This input current supply arrangement cooperates with theblocking action due to the polarity of magnetization of the core 27 toprevent more than one of the two amplifiers from being On at any giventime.

Considering the operation of this input circuit arrangement in detail,when an input signal is applied to transformer 41 having a polarity suchthat the upper terminal of secondary winding 40 as it appears in thedrawing, becomes negative with respect to the lower terminal, and havinga magnitude suflicient to overcome the bias of battery 39, that inputsignal tends to bias both emitters 35e and 36e positively with respectto their respective bases 35b and 36b, and thereby to cause a flow ofcurrent to the two emitters. As far as their emitter potentials areconcerned, either transistor may then turn on. However, the commoncurrent source (battery 38 and resistor 37) will supply current only tothe emitter whose potential is lowest. Due to the condition ofsaturation of core 27, only one of the two transistors can supplycurrent to the core in such a direction as to cause a large change influx and only that transistor will receive a feedback potential of theproper polarity to lower the potential of its base. The lowered basepotential of that one transistor will cause substantially all thecurrent from battery 38 to flow through its emitter. Hence the othertransistor will be cut off. Once the action is initiated, that onetransistor will, by virtue of the induced feedback voltage due to thechanging flux, continue to conduct substantial current until it drivesthe core to its opposite saturated state. Then the feedback will ceaseand both transistors will be oif until the next input signal.

The following table shows, by way of example, a particular set of valuesfor the potentials of the various batteries and for the impedance of thevarious resistors, in a circuit which has been operated successfully. Itwill be understood that these values are set forth by way of exampleonly and that the invention is not limited to these values or any ofthem. No value is given for the asymmetric impedance element 43, whichmay be considered to have substantially zero impedance in its forwarddirection and substantially infinite impedance in its reverse direction.

TABLE I Windings 28 and 29 turns 150 Windings 30, 31 and 32 do.. 20Resistor 37 ohms 3000 Battery 38 volts 15 Battery 39 d0 1%. Battery 49do 15 FIGURE 4 This figure illustrates a decimal counter circuitincluding four stages, each of which is generally equivalent to thebinary trigger circuit illustrated in FIGURE 3. The four stages arerespectively indicated by the reference numerals 52, 53, 54 and 55. Forthe most part, the individual circuit elements in each of the fourstages correspond exactly to their counter parts in FIGURE 3.Consequently, those elements have been given the same reference numeralsand will not be further described.

The output winding 32. of the stage 52 serves as an input winding forstage 53. Similarly, the output winding for stage 53 serves as an inputwinding for stage 54. The two amplifiers 33 and 34 in the final stage 55are provided with separate input circuits, instead of being connected toa common input circuit, as in the other stages. Amplifier 34 has itsinput circuit connected to the output winding 32 of stage 54, and theinput circuit of amplifier 33 is connected to a second output winding 56in stage 52. The final stage 55 is provided with two output windings,the normal output winding 32 which is connected to output terminals 57and 58 through an asymmetric impedance element 59, and a second outputwinding 60 which is connected through a wire 61 and an asymmetricimpedance element 62 to the input circuit of the second stage 53.

OPERATION OF FIGURE 4 Consider that a series of the input pulses arereceived at the input transformer 41 of stage 52. At the beginning ofthe series of pulses, the core 27 of stage 55 is magnetized in adirection such that the input pulses from winding 56 of stage 52 areineffective to make the amplifier 33 of stage 55 conductive. The inputpulses to amplifier 33 cannot then be effective until an input pulse isfirst received by the amplifier 34. The first eight of the input pulsesare counted by the stages 52, 53 and 54, and when the count of eight iscomplete, the stage 54 produces an output pulse of a polarity which isproper to make the amplifier 34 of stage 55 conductive. This producespotentials in output windings 32 and 60 of stage 55, but their polarityis such that they are blocked by the asymmetric units 59 and 62.Thereafter, on the tenth pulse, the amplifier 33 of stage 55 receives asignal pulse from winding 56 of stage 52. The amplifier 33 is theneffective to produce output pulses in the windings 32 and 60 of stage55, of the proper polarity to pass through the asymmetric units 59' and62.

The output pulse applied through winding 60 and wire 61 is effective inthe input of stage 53 to block the output pulse from stage 52 whichcorresponds to the tenth in the series of input pulses. The outputsignal produced at winding 32 in stage 55 is transmitted to the outputterminals 57 and 53, where it represents a decimal count of the inputsignals.

Reviewing the operation of the circuit of FIGURE 4 in more detail,FIGURE 5 illustrates graphically a series of ten input pulses 63, whichare applied through transformer 41 to the input stage 52. As describedabove, the pulses 63 produce output pulses 64 in winding 32 of stage 52,these output pulses being of alternately opposite polarities. The outputpulses are transmitted through output winding 32 of stage 52, to theinput circuits of stage '53. The negative pulses are of the wrongpolarity to produce any effect in stage 53. The positive pulses areeffective to actuate stage 53, producing in its output winding 32 signalpulses 65, which are also alternately of opposite polarities. Theseoutput pulses 65 are transmitted to the input circuits of stage 54. Thenegative output pulses are ineffective to actuate stage 54, but thepositive output pulses produce output signals 66 in output winding 32 ofstage 54. Summarizing, it may be seen that one positive output pulse 64is produced for each two input pulses 63, one positive output pulse 65is produced for each four input pulses 63, and one positive output pulse66 is produced for each eight input pulses '63. The three stages 52, 53and 54 therefore constitute a three order binary counter circuit.

The negative output pulse 66 from stage 54 is ineffective to actuatestage 55, since its polarity is in the wrong direction. However, thepositive output pulse 66 which corresponds to the eighth input pulse 63is effective to actuate the amplifier 34 in stage 55, in a sense toproduce a negative pulse 67 in output winding 32 of stage 55, whichnegative output pulse is suppressed by the asymmetric impedance elementor diode S9. The ninth input signal pulse 63 has no effect beyond thefirst stage, but the tenth input pulse is transmitted from the firststage through output winding 56 to the input circuit of amplifier 33 instage 55, where it is effective to actuate that stage to produce apositive output pulse 68 in each of windings 32 and 60. This positiveoutput pulse is transmitted through asymmetric impedance element 59 tothe output terminals 57 and 58, where it provides a decimal count of theinput signal pulses. It is also transmitted through wire '61 andasymmetric impedance element 62 to the input circuit of stage 53, whereit serves to counteract and suppress the corresponding output signal 64received from stage 52, so that the signal pulse is ineffective toactuate the stage 53, and the counter circuit is then ready to count thenext series of ten input pulses.

While we have shown and described certain preferred embodiments of ourinvention, other modifications thereof will readily occur to thoseskilled in the art and we therefore intend our invention to be limitedonly by the appended claims.

We claim:

[1. A binary trigger circuit comprising a memory device having asaturable magnetic core, a pair of saturating windings on said core, apair of saturating means, each including one of said windings, bothsaturating means being operable in response to input signals of limitedduration and of only one predetermined polarity to initiate a variationof the magnetic flux in the core in respectively opposite senses and tocontinue that variation to saturation, each of said saturating meansincluding limiting means effective to prevent operation of itsassociated saturating means when the core is saturated in its direction,means to deliver input signals of said limited duration andpredetermined polarity simultaneously to both said saturating means, sothat successive input signals are effective to saturate the corealternately in opposite directions, and signal output means responsiveto variation of the flux in the core in one sense only] [2. A binarytrigger circuit as defined in claim 1, in which said signal output meanscomprises another winding on said core] [3. A binary trigger circuitcomprising a memory device including a saturable magnetic core, meansfor saturating said core with magnetic flux in selectively opp sitedirections, including two driving windings on said core, two feedbackwindings on said core, two amplifying means, each including an outputcircuit and an input circuit, each of said output circuits including oneof said driving windings, each of said input circuits including one ofsaid feedback windings, the driving and feedback windings for eachamplifying means being connected to provide positive feedback, thefeedback windings for the respective amplifying means being connected toprovide feedback signals of opposite polarities upon a change inmagnetic flux in said core in a given sense, the driving windings beingconnected to vary the magnetic flux in the core in opposite senses inresponse to input signals of a predetermined polarity, and means forsupplying input signal pulses of limited duration and of said polaritysimultaneously to both input circuits, so that successive input signalsare etfective to saturate the core alternately in opposite directions,and signal output means responsive to variation of the flux in the corein one sense only] [4. A binary trigger circuit as defined in claim 3,in which each said amplifying means comprises a transistor operableselectively in On and Off conditions] [5. A binary trigger circuit asdefined in claim 4, in which each said transistor comprises an emitterelectrode; and including common biasing means for both emitterelectrodes including constant current supply means arranged to supplyonly sutficient current to maintain one transistor in its On condition]6. A binary counter circuit comprising: at least two binary triggerstages, each said trigger stage including a memory device having asaturable magnetic core, a pair of saturating windings on said core, apair of saturating means, each including one of said windings, bothsaturating means being operable in response to input signals of only onepredetermined polarity to vary the magnetic flux in the core inrespectively opposite senses and to the point of saturation, each ofsaid saturating means including limiting means effective to preventoperation of its associated saturating means when the core is saturatedin its direction; means to deliver input signals of said predeterminedpolarity simultaneously to both the saturating means of the first stage,so that successive input signals are effective to saturate the corealternately in opposite directions; coupling means including an outputwinding on the core of said first stage for transmitting output signalsof opposite polarities due to variation of the core flux of the firststage in opposite senses to both the saturating means of the secondstage, said second stage saturating means being responsive to signals ofone polarity only; and signal output means including an output windingon the core of said second stage and responsive to variation of the fiuxin the second stage core in one sense only.

7. A decimal counter circuit comprising four binary trigger stages, eachsaid trigger stage including a memory device having a saturable magneticcore, a pair of saturating windings on said core, a pair of saturatingmeans, each including one of said windings, both saturating means beingoperable in response to input signals of predetermined polarity to varythe magnetic flux in the core in respectively opposite senses and to thepoint of saturation, each of said saturating means including limitingmeans effective to prevent operation of its associated saturating meanswhen the core is saturated in its direction, means to deliver inputsignals of said predetermined polarity simultaneously to both thesaturating means of the first stage, so that successive input signalsare effective to saturate the core alternately in opposite directions;first and second coupling means including output windings on the coresof said first and second stages for transmitting output signals due tovariation of the core flux of each of said first and second stages toboth the saturating means of the succeeding stage; third coupling meansincluding an output winding on the core of the third stage fortransmitting output signals due to variation of the core flux of saidthird stage to one only of the saturating means of the fourth stage,fourth coupling means including a second output winding on the core ofthe first stage for transmitting output signals due to variation of thecore flux of the first stage to the other of the saturating means of thefourth stage, blocking means including an output winding on the core ofthe fourth stage for transmitting output signals due to variation of thecore flux of the fourth stage by said other saturating means to both thesaturating means of the second stage in a sense to block operationthereof, and signal output means including a second output winding onthe core of the fourth stage for transmitting output signals due tovariation of the core flux of the fourth stage by said other saturatingmeans.

125. A binary trigger circuit comprising amplifier means, means totransmit input signal pulses of limited duration to said amplifiermeans, a memory device shiftable between two distinct memory conditionsand stable in either of said conditions without the expenditure ofenergy, means including said amplifier means effective upon successiveinput signal pulses to shift said memory device alternately from onecondition to the other and back again, and signal output means operatedby said memory device to produce an output signal only when said deviceshifts from a particular one of said conditions to the other] [9. Abinary trigger circuit comprising transistor means, means to transmitinput signal pulses of limited duration to said transistor means, amemory device shiftable between two distinct memory conditions andstable in either of said conditions without the expenditure of energy,means including said transistor means effective upon successive inputsignal pulses to shift said memory device alternately from one conditionto the other and back again, and signal output means operated by saidmemory device to produce an output signal only when said device shiftsfrom one of said conditions to the other] ['10. A binary trigger circuitas defined in claim 9, wherein said memory device comprises a saturablemagnetic core and said two conditions comprise saturation of the corewith magnetic fields of oppositepolarities] [11. A binary triggercircuit as defined in claim 10, wherein said signal output meansincludes an output winding on said core, and means connected in serieswith said winding and effective to block output signals of one polarity][12. A magnetic memory device including a saturable magnetic core, meansfor saturating the said core with magnetic flux including a drivingwinding on said core and a feedback winding on said core, amplify-ingmeans including an output circuit and an input circuit, means normallyeffective to cut off substantially the flow of current in said outputcircuit, means connecting said driving winding electrically in saidoutput circuit, means connecting said feedback Winding electrically inboth said input and output circuits, said feed back winding beingarranged both magnetically and electrically, to provide positivefeedback, means independent of said feedback winding for supplying aninput pulse of limited duration to said input circuit, said driving andfeedback windings being effective in response to such an input signal toproduce in said driving winding a current continuing until the corebecomes saturated] [13. A magnetic memory device, including a saturablemagnetic core, means for saturating said core with magnetic flux inselectively opposite directions, including two driving windings on saidcore, two feed back windings on said core, two amplifying means, eachincluding an output circuit and an input circuit, means normallyeffective to cut off substantially the flow of current in both saidoutput circuits, each of said output circuits including one of saiddriving windings, each of said input circuits including one of saidfeedback windings, the driving and feedback windings for each amplifyingdevice being connected to provide positive feedback, the feedbackwindings for the respective amplifying means being connected to providefeedback signals of opposite polarities upon a change in magnetic fluxin said core in a given sense, the driving windings being connected tovary the magnetic flux in the core in opposite senses in response toinput signals of a predetermined polarity, and means external to saidfeedback windings for supplying input signals of limited durationsimultaneously to said input circuits, each of said signal beingeffective to turn on only one of said amplifying means, depending uponthe previous condition of saturation of the core, and each of saidamplifying means being effective when turned on to saturate the core inthe sense opposite to said previous condition] [14. A magnetic memorydevice as defined in claim 13, in which said feedback winding isconnected electrically in both said output and input circuits, and isarranged both magnetically and electrically for positive feedback] [15.A magnetic memory device as defined in claim 13, including an outputwinding on said core separate from said driving and feedback windings][16. A magnetic memory device as defined in claim 15, including meansconnected in series with said output winding to block signal pulses ofone polarity] 17. A binary trigger circuit comprising a memory deviceincluding a saturable magnetic core, means for saturating said core withmagnetic flux in selectively opposite directions, including two drivingwindings on said core, two feedback windings on said core, twoamplifying means, each comprising a transistor operable selectively inOn and Off conditions, each transistor having an emitter electrode,common biasing means for both emitter electrodes including constantcurrent supply means arranged to supply only sufficient current tomaintain one transistor in its On condition, each amplifying meansincluding an output circuit and an input circuit, each of said outputcircuits including one of said driving windings, each of said inputcircuits including one of said feedback windings, the driving andfeedback windings for each amplifying means being connected to providepositive feedback, the feedback windings for the respective amplifyingmeans being connected to provide feedback signals of opposite polaritiesupon a change in magnetic flux in said core in a given sense, thedriving windings being connected to vary the magnetic flux in the corein opposite senses in response to input signals of a predeterminedpolarity, and means for supplying input signal pulses of limitedduration and of said polarity simultaneously to both input circuits, sothat successive input signals are efiective to saturate the corealternately in opposite directions, and signal output means responsiveto variation of the flux in the core in one sense only.

18. A transistor wave-form generating circuit, comprising twotransistors, each having emitter, base and collector electrodes, atransformer having a primary winding and a secondary winding,non-resonant means connecting the primary winding and a source ofunidirectional electrical energy to a common terminal and in seriesbetween the collector and base electrodes of one of the transistors,non-resonant means connecting the collector electrode of the othertransistor to the common junction of the primary winding and saidsource, non-resonant means connecting the secondary winding in serieswith the base electrode of the other transistor, said transformer beingeffective in response to an increase in the current in said onetransistor to supply to the base electrode of the other transistor apotential tending to decrease the current flow therethrough from saidsource, means connecting the emitters of both transistors directly to ajunction, and means including a resistor and a second source ofelectrical energy in series connected between said junction and the baseelectrode of said one transistor.

References Cited in the file of this patent or the original patentUNITED STATES PATENTS 2,430,457 Dimond Nov. 11, 1947 2,584,811 PhelpsFeb. 5, 1952 2,591,406 Carter et a1 Apr. 1, 1952 2,605,306 Eberhard July29, 1952 2,620,448 Wallace Dec. 2, 1952 2,651,728 Wood Sept. 8, 19532,655,609 Shockley Oct. 13, 1953 2,682,615 Sziklai et al June 29, 1954

